As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin “fin” (or fin structure) extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Advantages of FinFET devices include reducing the short channel effect and higher current flow.
Because of the complexity inherent in nonplanar devices, such as FinFETs, a number of techniques used in manufacturing planar transistors are not available in manufacturing nonplanar devices. For example, stress-memorization techniques (SMTs) are applied in high-performance environments to improve nMOS devices. By carefully controlling the amorphization and re-crystallization of a planar device channel, the effects of a stress force applied to the device will remain even after the stressor is removed. The stress effects improve charge mobility through the channel, thereby improving device performance. What is needed is a method of applying SMTs to three-dimensional devices to obtain similar improvements in device performance.